1. Field of the Invention
The present invention relates to an image pickup device and an image pickup system, and more particularly, it relates to an image pickup device and an image pickup system, in which unit cells each comprising a plurality of photoelectric conversion regions, a plurality of transfer switch means provided in correspondence to the respective photoelectric conversion regions, and common amplifying means for amplifying photocarriers read from the plurality of photoelectric conversion regions as an input are arranged in a matrix pattern.
2. Related Background Art
In recent years, an image pickup device called as a CMOS sensor using a CMOS process has been paid attention to. The CMOS sensor has particularly been applied to a field of portable information equipments for the reasons that peripheral circuits can easily be mixed and driving can be performed with low voltage.
As a pixel arrangement of the CMOS sensor having a high S/N ratio, for example, as disclosed in Japanese Patent Application Laid-Open No. H11-122532 (1999), a pixel arrangement in which a transfer switch is provided between a photodiode and a pixel amplifier is known. However, a disadvantage of this arrangement is that, since the number of transistors is great, if the dimension of the pixel is reduced, it is difficult to leave an adequate area for the photodiode due to the existence of a substantial area required for the transistors. In order to eliminate this disadvantage, in recent years, for example, as disclosed in Japanese Patent Application Laid-Open No. H09-046596 (1997) (corresponding to U.S. Pat. No. 5,955,753), a technique in which the plurality of adjacent pixels hold the same transistor in common has been proposed. Such a conventional image pickup device is shown in FIG. 14 (same as FIG. 8 in the above patent document). In FIG. 14, the reference numeral 3 designates a transfer MOS transistor acting as a transfer switch; 4 designates a reset MOS transistor for supplying reset potential; and 5 designates a source follower amplifier MOS transistor. The reference numeral 6 designates a horizontal election MOS transistor for causing the source follower amplifier MOS transistor 5 to output a signal therefrom selectively; and 7 designates a load MOS transistor of the source follower. The reference numeral 8 designates a dark output transfer MOS transistor for transferring a dark output signal; and 9 designates a bright output transfer MOS transistor for transferring a bright output signal. The reference numeral 10 designates a dark output accumulating capacity CTN for accumulating the dark output signal; and 11 designates a bright output accumulating capacity CTS for accumulating the bright output signal. The reference numeral 12 designates a horizontal transfer MOS transistor for transferring the dark output signal and the bright output signal to a horizontal output line; and 13 designates a horizontal output line resetting MOS transistor for resetting the horizontal output line; 14 designates a differential output amplifier; 15 designates a horizontal scanning circuit; 16 designates a vertical scanning circuit; and 24 designates a pinned photodiode. Here, the dark output signal means a signal generated by resetting a gate region of the source follower amplifier MOS transistor 5 and the bright output signal means a signal obtained by adding a signal photo-electrically converted by the photodiode 24 to the dark output signal. A signal reducing dispersion in the source follower amplifier MOS transistors 5 is obtained from the differential output amplifier.
As can be seen from the above Figure, one source follower amplifier 5 is connected to two vertical photodiodes 24 via the transfer MOS transistors 3. Accordingly, although eight MOS transistors were required for two pixels in the prior art, since only five MOS transistors are used in this arrangement, it is advantageous for miniaturization. By holding the transistor in common, the number of the transistors per each pixel is reduced, thereby preserving an adequate area for the photodiode.
Further, as an example of the pixel layout having the common transistor arrangement, there is an arrangement disclosed in Japanese Patent Application Laid-Open No. 2000-232216 (corresponding to EP 1017106A).
As mentioned above, although the common transistor arrangement can effectively contribute to the reduction of the pixel, the Inventors found that, in the CMOS sensor having the common transistor arrangement, an aliasing called as blooming is apt to be generated, so that image quality is deteriorated considerably, particularly under a high luminance condition.